There has so far been known a technique in which, when converting a speech data signal as an analog signal, into a digital signal, by way of AD conversion, the speech data signal is sampled a preset number of times per preset time to digitize the speech data signal. In the case of speech signal, the higher the sampling frequency, the higher may be the pitch of the sound that may be recorded, such that up to the frequency component corresponding to one-half the sampling rate can be completely restored to the original analog signal.
Since the lower the sampling rate, the smaller may be the amount of data, there are occasions where, depending on the analog signal sampled, it is efficacious to record signal from the sound source as digital data at a low sampling rate. If a speech signal, digitized at a given sampling rate, is reproduced on an apparatus not coping with the sampling rate, the signal cannot be reproduced because of the difference in the sampling rate. For eliminating this inconvenience, there is known such a technique for converting a speech signal, digitized at a certain sampling rate, into a digital speech signal of a different sampling rate (see the Patent Document 1, as an example).
FIG. 1 depicts a block diagram showing the configuration of a sampling rate conversion apparatus, described in the Patent Document 1. In the sampling rate conversion between two clocks which are different in clock frequencies, shown in FIG. 1, the respective clock frequencies are dynamically changed in dependence upon temperature drift or jitter characteristic of an oscillator. In this sampling rate conversion apparatus, the frequency ratio R of the input and output clocks is calculated by a frequency detection unit J2 and, based on the result calculated, the sampling rate is converted by an fs conversion calculating unit J1. The frequency ratio R is found based on a count value of the rising edges of the input clock signal, with the output clock signal as a reference, that is, based on actual measured value.
The frequency detection unit J2, by itself, cannot cope with moderate change in the input clock frequency, thus leading to accumulated error, as a result of which underrun or overrun tends to be produced in the FIFO (First In First Out) J3. Hence, a margin detection unit J6 is provided to feed back the state of the FIFO J3 to the fs conversion calculating unit J1 to prevent underrun or overrun from occurring in the FIFO J3.
In the technique disclosed in Patent Document 1, a correction unit J5 is controlled from two places, namely the frequency detection unit J2 and the margin detection unit J6. On the other hand, with the configuration shown in FIG. 1, control from the margin detection unit J6 to the fs conversion calculating unit J1 is by a feedback loop. Such configuration tends to produce an unstable circuit operation. In addition, the apparatus is increased in size because it is necessary to provide circuit blocks, such as correction data generating unit J4, correction unit J5 or margin detection unit J6.
Hence, a sampling rate conversion apparatus, simplified in structure and high in operating accuracy, as the underrun or overrun in the FIFO J3 is prevented from occurrence, has been a desideratum.
[Patent Document 1]
Japanese Patent Kokai Publication No. JP-A-11-112440.